Generation framework for ultra-low power CGRAS
US12271671B2 · kind B2 · utility
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Key dates
| Filing date | Jan 11, 2022 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Oct 18, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a framework to generate ULP, energy-minimal coarse-grain reconfigurable arrays that execute in a spatial vector-dataflow fashion, mapping a dataflow graph spatially across a fabric of processing elements, applying the same DFG to many input data values, and routing intermediate values directly from producers to consumers. The spatial vector-dataflow minimizes instruction and data-movement energy and also eliminates unnecessary a switching activity because operations do not share execution hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.