Loop index set merging optimization for program instructions
US12271717B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2023 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Aug 24, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented method for merging loops. A number of processor units identifies loops in computer code. The loops are sequences of instructions that are repeated until conditions for the loops are reached. The number of processor units creates a tree comprising nodes that represent the loops and edges that represent relationships between nodes. The number of processor units utilizes the tree to identify a pair of candidate loops from sibling nodes. The number of processor units creates a new loop from the pair of candidate loops with an expanded iteration space based on iteration spaces for the pair of candidate loops in response to the pair of candidate loops being eligible for merging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.