Semiconductor device and semiconductor system
US12272400B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2023 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Sep 10, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a memory array having a plurality of associative memory cells arranged in a matrix form for storing entries. The memory array is divided into a plurality of memory blocks for sequentially performing a retrieval operation along a column direction, and further includes a plurality of match lines corresponding to the respective memory blocks and provided correspondingly to each memory cell row, a plurality of search lines corresponding to the respective memory blocks and provided correspondingly to each memory cell column, and a plurality of match amplifiers corresponding to the respective memory blocks and provided to the plurality of match lines. The match line provided correspondingly to the preceding memory block is set to become shorter than the match line provided correspondingly to the subsequent memory block. The memory array further includes a timing control unit for controlling timing for driving the search line of the subsequent memory block based on a length of the match line provided correspondingly to the preceding memory block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.