Methods of operating a near memory processing-dual in-line memory module (NMP-DIMM) for performing a read operation and an adaptive latency module and a system thereof
US12272423B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2022 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Jan 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a Near Memory Processing-Dual In-line Memory (NMP-DIMM) system, the method including: determining, by an adaptive latency module of the NMP-DIMM system, a synchronized read latency value for performing a read operation upon receiving a Multi-Purpose Register (MPR) read instruction from a host device communicatively connected with the NMP-DIMM system, wherein the MPR read instruction is received from the host device for training the NMP-DIMM system, wherein the synchronized read latency value is determined based on one or more read latency values associated with one or more memory units of the NMP-DIMM system; and synchronizing, by the adaptive latency module, one or more first type data paths and a second type data path in the NMP-DIMM system based on the determined synchronized read latency value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.