Gate driving technique to lower switch on-resistance in switching converter applications
US12273021B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2024 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Jan 24, 2044 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Techniques and apparatus for driving transistor gates of a switched-mode power supply (SMPS) circuit. One example power supply circuit generally includes a switching converter having a switching transistor and a gate driver having an output coupled to a gate of the switching transistor. The gate driver includes a first switching device coupled between the output of the gate driver and a first voltage rail; a second switching device coupled between the output of the gate driver and a voltage node of the gate driver; a third switching device coupled between the voltage node of the gate driver and a second voltage rail; and a voltage clamp coupled in series with a fourth switching device, the voltage clamp and the fourth switching device being coupled between a third voltage rail and the voltage node (or the output of the gate driver).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.