Error correction code decoder, storage controller and storage device
US12273127B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2023 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Oct 8, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1044
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An Error correction code (ECC) decoder including an input manager configured to sequentially receive a first read data including a plurality of data units read from a plurality of sectors in a memory cell array of a nonvolatile memory device, by unit of sector, a pre-decoder configured to sequentially receive the first read data and generate a respective syndrome of each of the data units, and a main decoder configured to sequentially perform a first ECC decoding on the first read data based on the respective syndrome. The input manager includes a defective sector buffer to store a data unit having a minimum expected error count from among data units on which a first ECC decoding is failed. The main decoder performs a second ECC decoding on a defective data unit stored in the defective sector buffer and receives a second read data from a selected sector corresponding to the defective data unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.