Three-dimensional semiconductor memory device and electronic system including the same
US12274062B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2022 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Oct 11, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/689
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional semiconductor memory device may include a source structure on a substrate, a stack structure including electrode layers and inter-electrode insulating layers, which are on the source structure and are alternately stacked, a vertical structure penetrating the stack structure and the source structure and being adjacent to the substrate, and a separation insulation pattern penetrating the stack structure and the source structure and being spaced apart from the vertical structure. The uppermost one of the inter-electrode insulating layers may include a first impurity injection region located at a first height from a top surface of the substrate. The stack structure may define a groove, in which the separation insulation pattern is located. An inner sidewall of the groove may define a recess region, which is located at the first height from the top surface of the substrate and is recessed toward the vertical structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.