Method of manufacturing MRAM device with enhanced etch control
US12274176B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2023 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Aug 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
Abstract
A method of manufacturing a semiconductor device includes: forming a substrate over the substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.