Array substrate and display panel
US12276892B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2024 |
| Grant date | Apr 15, 2025 |
| Priority date | — |
| Expiry date | Apr 20, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Some embodiments of the present disclosure provide an array substrate and a display pane. Multiple pixel electrode branches in a corresponding one of the pixel regions are divided into a first pixel electrode branch and a second pixel electrode branch by a corresponding one of the metal common electrodes. The first pixel electrode branch and the second pixel electrode branch, which are located in the same pixel regions, are connected to different TFTs. In each pixel region, an end of the first pixel electrode branch close to a corresponding one of the scan lines is connected to a corresponding one of the TFTs, and an end of the second pixel electrode branch close to another corresponding one of the scan lines is connected to another corresponding one of the TFTs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.