Automatic generation of processing architecture-specific algorithms
US12277051B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 5, 2024 |
| Grant date | Apr 15, 2025 |
| Priority date | — |
| Expiry date | Feb 5, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/447
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of generating automatically architecture-specific algorithms, comprising receiving an architecture independent algorithm and one or more algorithm parameters defining at least a target processing architecture and a format of an output of an architecture-specific algorithm implementing the received algorithm, determining automatically a functionality of the algorithm by analyzing the algorithm, selecting one or more architecture-specific computing blocks of the target processing architecture according to the functionality of the algorithm and the algorithm parameter(s) wherein each computing block is dynamically reconfigurable in runtime and associated with (1) simulation code simulating its functionality, and (2) execution code executing its functionality, testing an emulated architecture-specific algorithm constructed using the simulation code of the selected architecture-specific computing block(s) to verify compliance with the algorithm parameter(s), and, responsive to successful compliance verification, generating automatically an architecture-specific code segment implementing the architecture-specific algorithm based on the execution code of the selected architecture…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.