ONON sidewall structure for memory device and method for making the same
US12277977B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2024 |
| Grant date | Apr 15, 2025 |
| Priority date | — |
| Expiry date | May 13, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.