Manufacturing method of semiconductor structure
US12278114B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2022 |
| Grant date | Apr 15, 2025 |
| Priority date | — |
| Expiry date | Jul 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a manufacturing method of a semiconductor structure, including: an insulating layer includes a first dielectric layer and a second dielectric layer, a protective layer covers an upper surface of the second dielectric layer and a bottom and sidewalls of the first trench; removing part of the protective layer to expose at least part of a surface of the second dielectric layer; removing the second dielectric layer by a first wet etching process, the first wet etching process has a first etch selectivity of a material of the second dielectric layer to that of the first dielectric layer; and removing the protective layer by a second wet etching process, the second wet etching process has a second etch selectivity of a material of the protective layer to that of the first dielectric layer, and the second etch selectivity is greater than the first etch selectivity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.