Platform power integrity design including package standard power integrity model and compact voltage regulator module model
US12278175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2021 |
| Grant date | Apr 15, 2025 |
| Priority date | — |
| Expiry date | Aug 16, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes an integrated circuit having a die; a package substrate; first conductive connections coupled between the die and a first side of the package substrate; second conductive connections located on a second side of the package substrate opposite from the first side. The second conductive connections are coupled to the first conductive connections through conductive paths in the package substrate. The first conductive connections and the conductive connections are associated with an S-parameter of an electrical model of the integrated circuit package. The electrical model further includes at least one of a current value associated with a power rail of the integrated circuit package, an impedance target associated with a location at the integrated circuit package, and a mapping associated with the first and second conductive connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.