Methods of manufacturing semiconductor devices
US12278270B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2020 |
| Grant date | Apr 15, 2025 |
| Priority date | — |
| Expiry date | Jan 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method forms a part of a power semiconductor device. The method includes homoepitaxially forming two silicon carbide layers on a first side of a silicon carbide substrate and forming a pattern of pits on a second side of the silicon carbide substrate. The two layers include a buffer layer, on the first side of the silicon carbide substrate, and have a same doping type of the silicon carbide substrate and a doping concentration equal to or greater than 1017 cm−3 in order to increase the quality of at least one subsequent SiC layer. The two layers include an etch stopper layer, being deposited on the buffer layer and has a same doping type as the buffer layer but a lower doping concentration in order to block a trenching process. The pattern of pits, obtained by electrochemical etching, extends completely thorough the silicon carbide substrate and the buffer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.