Bias techniques for amplifiers with mixed polarity transistor stacks
US12278597B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 12, 2023 |
| Grant date | Apr 15, 2025 |
| Priority date | — |
| Expiry date | Jul 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/30117
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various methods and circuital arrangements for biasing gates of stacked transistor amplifier that includes two series connected transistor stacks of different polarities are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback error voltage that is based on a sensed voltage at a common node of the two series connected transistor stacks. According to one aspect, gate biasing voltages to input transistors of each of the two series connected stacks are adjusted by respective current mirrors that are controlled based on the feedback error voltage. According to another aspect, other gate biasing voltages are generated by maintaining a fixed gate biasing voltage between any two consecutive gate basing voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.