ADC apparatus and control method
US12278644B2 · kind B2 · utility
0Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Jun 15, 2023 |
| Grant date | Apr 15, 2025 |
| Priority date | — |
| Expiry date | Nov 13, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a high gain input stage configured as an integrator in a successive approximation register (SAR) analog-to-digital converter (ADC), a clamping and filtering stage configured to clamp a voltage on a high impedance node to a predetermined level approximately equal to a diode voltage drop in a clamping mode of an SAR cycle, and a decision-making stage connected to an output of the clamping and filtering stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.