System and method for transistor pathogen detector
US12282018B2 · kind B2 · utility
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Key dates
| Filing date | Jun 5, 2024 |
| Grant date | Apr 22, 2025 |
| Priority date | — |
| Expiry date | Jun 5, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N2333/165
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed herein is a system and method for transistor pathogen virus detector in which one embodiment may include a substrate layer, a silicon dioxide layer on the substrate layer, a nanocrystalline diamond layer on the silicon dioxide layer, a graphene oxide layer on the nanocrystalline diamond layer, fluorinated graphene oxide portions; and a linker layer, the linker layer including a plurality of pathogen receptors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.