System for characterizing a transistor circuit
US12282054B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2023 |
| Grant date | Apr 22, 2025 |
| Priority date | — |
| Expiry date | Nov 2, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K10/46
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system for characterizing a transistor circuit which has a local minimum in its transfer characteristic by finding its local minimum. The system comprises: a bias voltage generator for generating a toggling signal; a multiplier configured for multiplying an electrical signal which is a function of the drain source current of the transistor circuit, with a waveform alternating between two predefined values synchronously with the toggling signal; a first integrator configured for integrating the electrical signal from the multiplier, and wherein if more integrators are present, linear combinations of output signals of the integrators are provided to the further integrators; a summator configured for summing the toggling signal and an integration signal and configured for outputting the sum to the gate of the transistor circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.