Hardware-assisted core frequency and voltage scaling in a poll mode idle loop
US12282377B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Jun 25, 2021 |
| Grant date | Apr 22, 2025 |
| Priority date | — |
| Expiry date | Aug 24, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.