Interconnects between chiplets and related link initialization protocols
US12282392B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2023 |
| Grant date | Apr 22, 2025 |
| Priority date | — |
| Expiry date | Dec 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provides various systems, apparatuses, and techniques for reducing latencies and power consumption of link training or retraining. In some aspects, the techniques use a specific register to identify the cause of link retraining. Based on the identified reasons of link retraining, the apparatus can selectively skip the initialization of certain redundant lanes of the link. In some aspects, the Universal Chiplet Interconnect Express (UCIe) Link Training and Status State Machine (LTSSM) can be configured to identify whether link retraining is initiated as part of a trainerror or linkerror exit or not. A UCIe device can have a redundant_recovery (RR) register that can be set to different values to identify the cause of link retraining (e.g., due to trainerror/linkerror or not).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.