Securing on-chip communication using digital watermarking
US12282543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2021 |
| Grant date | Apr 22, 2025 |
| Priority date | — |
| Expiry date | Jul 6, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/608
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes digital watermark detection systems and methods. In one such system, a plurality of intellectual property cores are integrated on a system-on-chip, such that the intellectual property cores comprise a first intellectual property core and a second intellectual property core. The system further includes a first network interface connected to the first intellectual property core that can encode a first digital watermark into a packet stream designated for the second intellectual property core. The system further includes a second network interface connected to the second intellectual property core that can receive the packet stream and decode the packet stream to generate a second digital watermark. The second network interface is further configured to perform a validation test on the packet stream and deliver the packet stream to the second intellectual property core when the first digital watermark is determined to match the second digital watermark.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.