Vector processor utilizing massively fused operations
US12282774B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2021 |
| Grant date | Apr 22, 2025 |
| Priority date | — |
| Expiry date | Aug 24, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for the use of fused vector processor instructions by a vector processor architecture. Each fused vector processor instruction may include a set of fields associated with individual vector processing instructions. The vector processor architecture may implement local buffers facilitating a single vector processor instruction to be used to execute each of the individual vector processing instructions without re-accessing vector registers between each executed individual vector processing instruction. The vector processor architecture enables less communication across the interconnection network, thereby increasing interconnection network bandwidth and the speed of computations, and decreasing power usage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.