Pulse generator, error check and scrub (ECS) circuit and memory
US12283345B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2023 |
| Grant date | Apr 22, 2025 |
| Priority date | — |
| Expiry date | Sep 16, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pulse generator, an Error Check and Scrub (ECS) circuit and a memory are provided. The pulse generator includes: a delay circuit configured to receive an ECS command signal, perform delay processing on the ECS command signal, and output a delay command signal, the delay between the ECS command signal and the delay command signal being a first preset value; and a latch circuit configured to receive the ECS command signal and the delay command signal, perform latch processing based on the ECS command signal and the delay command signal, and output an ECS pulse signal. The pulse width of the ECS command signal is provided with a plurality of values, and the pulse width of the ECS pulse signal is the first preset value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.