Method for forming semiconductor structure
US12283517B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 8, 2021 |
| Grant date | Apr 22, 2025 |
| Priority date | — |
| Expiry date | Feb 22, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0156
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base, a dummy gate structure, a source-drain doped region, and an interlayer dielectric layer; removing the dummy gate structure located at an isolation region to form an isolation opening; performing first ion doping on a fin below the isolation opening, to form an isolation doped region, where a doping type of the isolation doped region is different from a doping type of the source-drain doped region; filling an isolation structure in the isolation opening; removing the remaining dummy gate structure, to form a gate opening; and forming a gate structure in the gate opening. In embodiments and implementations of the present disclosure, the isolation doped region with a doping type different from that of the source-drain doped region is formed, so that a doping concentration of opposite-type ions in the fin of the isolation region can be improved, thereby accordingly improving a potential energy barrier of a P-N junction formed by the source-drain doped region and the fin of the isolation region, to prevent a conduction current from being generated in the fin of the isolation reg…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.