Interface device and signal transceiving method thereof
US12283957B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 31, 2022 |
| Grant date | Apr 22, 2025 |
| Priority date | — |
| Expiry date | Aug 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interface device and a signal transceiving method thereof are provided. The interface device includes a slave circuit and a master circuit. The slave circuit is coupled to the master circuit and includes a first programmable delay line, a first output clock generator, and a first phase detector. The first programmable delay line provides a first adjusting delay amount according to a first adjust signal, and generates a first delayed clock signal by delaying a first clock signal according to the first adjusting delay amount. The first output clock generator generates a second clock signal according to the first delayed clock signal. The first phase detector detects a phase difference of the first clock signal and the second clock signal to generate first phase lead or lag information. The first adjust signal is generated according to the first phase lead or lag information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.