Array substrate and display panel
US12284876B2 · kind B2 · utility
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2References
20Claims
0Family size
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Key dates
| Filing date | Mar 31, 2024 |
| Grant date | Apr 22, 2025 |
| Priority date | — |
| Expiry date | Mar 31, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/124
Abstract
An array substrate and a display panel are provided. A driving circuit layer of the array substrate includes a low temperature polysilicon thin film transistor and a low temperature polycrystalline oxide thin film transistor which are electrically connected with each other. A hydrogen blocking layer is formed on at least one of an upper side and a lower side of an oxide active layer of the low temperature polysilicon thin film transistor. The hydrogen blocking layer can block hydrogen ions in other film layers to invade the oxide active layer and avoid that device characteristics are drifted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.