Voltage hold circuit, voltage monitoring circuit, and semiconductor integrated circuit
US12287356B2 · kind B2 · utility
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3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 17, 2022 |
| Grant date | Apr 29, 2025 |
| Priority date | — |
| Expiry date | Dec 17, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/16552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The voltage hold circuit is a voltage hold circuit configured to operate every processing cycle, the processing cycle including a hold period and a reset period following the hold period, and hold a voltage value for an input voltage signal, the voltage hold circuit including: a first hold circuit configured to operate to hold a minimum voltage value for the input voltage signal in the hold period every the processing cycle; and a second hold circuit configured to operate to hold a maximum voltage value for the input voltage signal in the reset period every the processing cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.