Self-correcting circuitry
US12287369B1 · kind B1 · utility
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18Claims
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Key dates
| Filing date | Aug 2, 2023 |
| Grant date | Apr 29, 2025 |
| Priority date | — |
| Expiry date | Aug 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Embodiments include herein are directed towards various circuit topologies. A self-correcting latch circuit may include a plurality of memory loops, a plurality of clock inputs, a plurality of data inputs, and a plurality of outputs. Each of the plurality of memory loops may be configured to store data in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.