High-speed low-latency interconnect interface (HLII) for silicon interposer interconnection
US12287748B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2023 |
| Grant date | Apr 29, 2025 |
| Priority date | — |
| Expiry date | Sep 18, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-speed low-latency interconnect interface (HLII) for silicon interposer interconnection is provided. The HLII is configured to perform large-scale input/output (I/O) interconnection on a silicon interposer, and includes a physical link (PL) and an LL (LL). The LL receives a data signal, a configuration signal, and a control signal of logical resource inside a chiplet, and can complete data conversion, parity check, training, channel repair, instruction stream generation, and other functions for the PL. The PL receives and transmits a data signal converted by the LL. The PL includes a high-speed I/O port, a first input first output (FIFO), and related control logic. The high-speed I/O port of the PL is compatible with both a double date rate (DDR) transmission mode and a single data rate (SDR) transmission mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.