Interface circuit and memory controller
US12287973B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 24, 2023 |
| Grant date | Apr 29, 2025 |
| Priority date | — |
| Expiry date | Jan 10, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface circuit includes multiple signal processing devices and a monitor and calibration module. A process monitor monitors a current or a voltage of a test element to generate a process detection result. A temperature monitor monitors an environment temperature to generate a temperature monitored result. A calibration circuit performs calibration operation on a signal processing device according to a preferred reference value subset to adjust a characteristic value of the signal processing device. A compensation control mechanism operation logic selects the preferred reference value subset from multiple reference value subsets according to the process detection result and the temperature monitored result and generates a calibration control signal to control the calibration operation of the calibration circuit. The compensation control mechanism operation logic includes a subset handle interface which generates a subset read control signal and transmits the subset read control signal to a corresponding storage circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.