Semiconductor memory device and method of operating the same
US12288578B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2022 |
| Grant date | Apr 29, 2025 |
| Priority date | — |
| Expiry date | Jul 21, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit, and a refresh control circuit. The row hammer management circuit captures row addresses accompanied by first active commands randomly selected from active commands, each of which has a first selection probability that is uniform, from an external memory controller during a reference time interval, and selects at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.