Critical dimension error analysis method

US12288725B2 · kind B2 · utility

Assignee

• SHANGHAI IC R&D CENTER CO., LTD. · CN

Inventors

• Xueru YU · Shanghai, CN
• Hongxia SUN · Miaocheng, CN
• Chen Li · Zhunan Town, TW
• Pengfei Wang · Shanghai, CN
• Jiebin Duan · Shanghai, CN
• Xiucui Wang · Shanghai, CN
• Hao FU · Shanghai, CN
• Tao Zhou · Daguantang, CN
• Yan Yan · Shanghai, CN
• Bowen Xu
• Lingyi Guo · Shanghai, CN
• Liren Li · Tianjin, CN

Key dates

• Filing date: Jul 23, 2020
• Grant date: Apr 29, 2025
• Expiry date: Dec 3, 2041

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P90/30
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present invention disclosures a critical dimension error analysis method, comprising: S01: performing lithography processes on a wafer, measuring the critical dimension (CD) values of the test points in each of the fields respectively; M and N are integers greater than 1; S02: removing extreme outliers from the critical dimension (CD) values; S03: rebuilding remaining CD values by a reconstruction model fitting method, and obtaining rebuilt critical dimension (CD″) values, according to relative error between CD″ and CD, dividing the rebuilt critical dimension (CD″) values into scenes and the number of the scenes is A; S04: calculating components and corresponding residuals of the test points in each of the scenes under a reference system corresponding to a correction model by parameter estimation; S05: modifying machine parameters and masks by the correction model according to above calculation results. The present invention uses an outer limit to remove extreme outliers, so as to analyze a critical dimension error during a lithography process quickly and accurately.