Semiconductor package
US12288743B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2022 |
| Grant date | Apr 29, 2025 |
| Priority date | — |
| Expiry date | Mar 12, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73204
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a lower substrate that includes a lower wiring layer; a semiconductor chip disposed on the lower substrate, and an upper substrate disposed on the semiconductor chip. The upper substrate includes a lower surface that faces the semiconductor chip, an upper wiring layer, and a plurality of protruding structures disposed below the lower surface. The lower surface of the upper substrate includes a cavity region that overlaps the semiconductor chip in a first direction, and a plurality of channel regions that extend from the cavity region to an edge of the upper substrate. The cavity region and the plurality of channel regions are defined by the plurality of protruding structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.