Low-power retention flip-flop
US12289107B2 · kind B2 · utility
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9References
12Claims
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Key dates
| Filing date | Dec 13, 2021 |
| Grant date | Apr 29, 2025 |
| Priority date | — |
| Expiry date | Dec 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low-power retention flip-flop is provided. The low-power retention flip-flop may include: a master latch configured to output an input signal based on first control signals; a slave latch configured to output the signal from the master latch based on second control signals; and a control logic configured to generate the first control signals based on a clock signal, and provide the generated first control signals to the master latch, and generate the second control signals based on the clock signal and a power down mode signal, and provide the generated second control signals to the slave latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.