Syntonization through physical layer of interconnects
US12289388B2 · kind B2 · utility
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78References
28Claims
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Key dates
| Filing date | Jul 20, 2022 |
| Grant date | Apr 29, 2025 |
| Priority date | — |
| Expiry date | Nov 5, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a clock syntonization system includes a first compute node including a first physical hardware clock to operate at a first clock frequency, a second compute node, and an interconnect data bus to transfer data from the first compute node at a data rate indicative of the first clock frequency of the first physical hardware clock, and wherein the second compute node includes clock synchronization circuitry to derive a second clock frequency from the data rate of the transferred data, and provide a clock signal at the derived second clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.