Memory device
US12289888B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2022 |
| Grant date | Apr 29, 2025 |
| Priority date | — |
| Expiry date | Oct 16, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.