Cache synchronization for chiplet accelerators
US12292836B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Mar 22, 2023 |
| Grant date | May 6, 2025 |
| Priority date | — |
| Expiry date | Mar 23, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/502
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A chiplet-based architecture provides for a reduction in cache synchronization operations by tracking a relationship between chiplet execution kernels and array operands to elide synchronization when particular arrays are not in use in the caches of other chiplets or when the current target chiplet already has the array operand. Further efficiency is promoted in some embodiments by assigning chiplets for reuse based on previously received arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.