Static random-access memory (SRAM) apparatus and method for reducing wire delay
US12293806B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2022 |
| Grant date | May 6, 2025 |
| Priority date | — |
| Expiry date | Mar 31, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various example embodiments of the inventive concepts include a SRAM apparatus including a left memory array and right memory array, each of the left memory array and the right memory array including a left memory array and a right memory array, each comprising a plurality of columns, the plurality of columns in each of the left memory array and the right memory array divided into a plurality of segments, and each of the segments comprising a plurality of memory bit cells, and central driver circuitry comprising a plurality of driver devices, each of the plurality of driver devices communicatively connected to a corresponding segment of the plurality of segments through a corresponding metal control line of a plurality of metal control lines, the central driver circuitry configured to route at least one array signal to at least one segment of the plurality of segments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.