Method for packaging stacking flip chip
US12293984B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2024 |
| Grant date | May 6, 2025 |
| Priority date | — |
| Expiry date | Sep 12, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/92125
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present application is applicable to the field of semiconductor technology and provides a method for packaging stacking a flip chip, which includes: placing a filling template on a substrate, the filling template being provided with a through hole of a preset pattern; filling a filling material into the through hole of the filling template, and after the filling material being formed on the substrate, removing the filling template; placing a chip with solder balls on the substrate formed with the filling material, such that at least a portion of the solder balls being covered by the filling material; and connecting the chip to the substrate through the solder balls, and curing the filling material with air gaps formed between the at least a portion of the solder balls covered with the filling material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.