Differential clock duty cycle corrector circuits
US12294376B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2022 |
| Grant date | May 6, 2025 |
| Priority date | — |
| Expiry date | Nov 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for differential clock duty cycle correction. For example, a method includes converting an input rail-to-rail differential clock signal to a low-swing differential signal; fixing a DC bias level of the low-swing differential signal; changing DC bias levels of ends of the low-swing differential signal in a complementary manner to change cross-over points of the low-swing differential signal; and inputting the low-swing differential signal to a level shifter and buffer to generate a duty-corrected rail-to-rail digital differential clock signal. For example, an apparatus may include a differential pair of CMOS transmission-gate switches as clock input switches; complementary differential pairs of transistors with gate terminals connected to a differential control voltage signal; and/or extra current sources for independently controlling the DC bias voltages of ends of a differential clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.