Offset calibration method and circuit applied to comparator array
US12294378B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2025 |
| Grant date | May 6, 2025 |
| Priority date | — |
| Expiry date | Jan 7, 2045 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed are an offset calibration method and circuit applied to a comparator array. The offset calibration circuit includes a global calibration voltage generation module, integrators, comparators, a global logic control circuit, and local logic control circuits; an entire comparator array shares the single global calibration voltage generation module, and each of the comparators only needs to introduce an integrator circuit, such that a large calibration range and a small calibration step are achieved, a long calibration cycle and a large circuit area are required, and the requirements for a low area are satisfied. The offset calibration method provided by the present disclosure is similar to a binary search algorithm, which is adopted to search for the offset voltage, the calibration step of can be realized by only N cycles, and short calibration time is thus realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.