Optimizations of memory-utilization and PCM processing schedules for an LDPC decoder
US12294386B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | Sep 7, 2023 |
| Grant date | May 6, 2025 |
| Priority date | — |
| Expiry date | Sep 7, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6566
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The disclosure generally relates to improvements of a log-likelihood ratios (LLRs) memory structure and memory capacity of a decoding hardware (also referred to as a decoder) in decoding a sequence of codewords encoded with a low-density parity-check (LDPC) code (e.g. a quasi-cyclic (QC) LDPC code). Further, the disclosure relates to the optimization of a processing schedule of a parity check matrix (PCM) describing the LDPC code so as to reduce or minimize the number of patch LLRs that need to be (simultaneously) stored in an LLR memory of a decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.