Memory device with metal pad pattern and system including the same
US12295141B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2021 |
| Grant date | May 6, 2025 |
| Priority date | — |
| Expiry date | Nov 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes a lower structure, a stacked structure on the lower structure, the stacked structure including horizontal layers and interlayer insulating layers alternately stacked in a vertical direction, and each of the horizontal layers including a gate electrode, a vertical structure penetrating through the stacked structure in the vertical direction, the vertical structure having a core region, a pad pattern with a pad metal pattern on the core region, a dielectric structure including a first portion facing a side surface of the core region, a second portion facing at least a portion of a side surface of the pad metal pattern, and a data storage layer, and a channel layer between the dielectric structure and the core region, a contact structure on the vertical structure, and a conductive line on the contact structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.