Performance level control in a data processing apparatus
US12298833B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2020 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Dec 25, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.