Memory cell array unit
US12298869B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | Oct 7, 2021 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Oct 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/805
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell array unit according to an embodiment of the present disclosure includes a memory cell array and a microcontroller. The memory cell array includes an n-bit allocation bit allocated from a memory controller in read/write control, and a redundant bit of one or a plurality of bits not being provided with a switching mechanism that switches as a substitution for a portion of the allocation bit. The microcontroller reads and writes n-bit data from and into the memory cell array using the allocation bit and the redundant bit on the basis of the read/write control from the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.