Architectural support for persistent applications
US12298897B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 4, 2022 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Jul 16, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/304
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Illustrative embodiments are directed to methods, apparatus and computer program products for caching at least a fraction of data stored in a non-volatile memory in a mirror region of a dynamic random access memory. A memory controller hub of a processor chip coupled to both the non-volatile memory and the dynamic random access memory is configured to, when an update to the dynamic random access memory is cached in the mirror region of the dynamic random access memory, use the memory controller hub to write the update directly to the mirror region of the dynamic random access memory and concurrently mirror the update to the non-volatile memory to provide coherent persistent durability of the update. When a read from the dynamic random access memory is cached in the mirror region of the dynamic random access memory, embodiments can use the memory controller hub to serve the read directly from the mirror region of the dynamic random access memory to optimize read operations of persistent objects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.