Enhanced write buffer flush scheme for memory devices with high density storage memory architecture
US12298912B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2023 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Nov 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes maintaining a list of data segments stored in a write buffer having a single-level cell memory architecture. The list includes, for each entry of the list, a data segment identifier of a respective data segment and an available contiguous memory space in the write buffer if the data segment is flushed. The list is sorted based on the available contiguous memory space. The method includes detecting a flush opportunity and initiating, based on the detecting, a flush operation to write a first data segment that corresponds to a first entry of the list from the write buffer to a memory module having a higher storage density memory architecture. Other aspects and features are also claimed and described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.