Method of manufacturing a semiconductor device
US12299368B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2021 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Nov 23, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device is disclosed. The method includes generating a first virtual layout by placing and routing standard cells using a virtual netlist, searching first duplicate pattern regions in the first virtual layout and choosing one of them as a first representative pattern region, performing an OPC operation on the first representative pattern region to obtain a first OPC result, generating an actual layout by placing and routing standard cells using an actual netlist, performing an OPC operation on the actual layout, and forming a photoresist pattern on a substrate using a photomask manufactured based on the actual layout, to which the OPC operation is applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.