Bandwidth-aware computational graph mapping
US12299424B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2023 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Jul 10, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7871
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method of transforming a high-level program for mapping onto a coarse-grained reconfigurable (CGR) processor with an array of CGR units, including sectioning a dataflow graph into a plurality of sections; extracting performance information for each of the plurality of sections; on a CGR unit: assigning to a section at least two computations dependent on a first data element; scheduling an additional load of the first data element in response to available memory bandwidth for that section; eliminating a buffer between the additional load of the first data element and one of the two computations, for that section; generating configuration data for the placed positions and the routed data and communication channels, wherein the configuration data, when loaded onto an instance of the array of CGR units, causes the array of CGR units to implement the dataflow graph; and storing the configuration data in a non-transitory computer-readable storage medium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.