Nonvolatile memory devices
US12300302B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2024 |
| Grant date | May 13, 2025 |
| Priority date | — |
| Expiry date | Feb 19, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.